Kwang-Ting CHENG, HKUST, IEEE Fellow

Bio:

   Prof. Tim CHENG Kwang-Ting was appointed Vice-President for Research and Development with effect from April 1, 2022. He joined HKUST in May 2016 as the Dean of Engineering, in concurrence with his appointment as Chair Professor jointly in the Department of Electronic and Computer Engineering and in the Department of Computer Science and Engineering.

   He graduated from University of California, Berkeley in 1988 with a PhD in Electrical Engineering and Computer Sciences. Before joining HKUST, he was a Professor of Electrical and Computer Engineering (ECE) at the University of California, Santa Barbara (UCSB), where he served since 1993. Prior to teaching at UC Santa Barbara, he spent five years at AT&T Bell Laboratories.

   At UC Santa Barbara, Prof. Cheng had taken up various important academic leadership roles, such as Founding Director of the Computer Engineering Program from 1999 to 2002, Chair of Department of ECE from 2005 to 2008, Acting Associate Vice-Chancellor for Research in 2013 and Associate Vice-Chancellor for Research from 2014 to 2016 where he helped oversee the research development, infrastructure, and compliance of UCSB’s research enterprise with over US$200 million extramural research funding.

   A highly respected teacher-scholar and internationally leading researcher with excellent experience in fostering cross-disciplinary research collaboration, Prof. Cheng is a world authority in the field of electronics testing and design verification, as well as an impactful contributor across a wide range of research areas including design automation of electronic and photonic systems, computer vision, and medical image analysis. He had previously served as Director of the US Department of Defense Multidisciplinary University Research Initiative (MURI) Center for 3D Hybrid Circuits which integrated CMOS and nano-memristors for future computing systems. He has published more than 500 technical papers, co-authored five books, held 12 US patents, and transferred several of his inventions into successful commercial products. He is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) and Hong Kong Academy of Engineering Sciences (HKAES). His works are of high impact with due recognition from the field, including 12 best paper awards and one Distinguished Paper Citation in major conferences and journals, as well as a Pan Wen Yuan Foundation Award for Outstanding Research. He was also recognized in the 50th Design Automation Conference (DAC) in 2013 as a Top 10 Author in DAC’s Fourth Decade and a Prolific Author.

   Prof. Cheng has been very active in providing professional services to the IEEE and to the academic community at large. Having served as the editor-in-chief of IEEE Design & Test of Computers, on the boards of IEEE Council on Electronic Design Automation’s Board of Governors and IEEE Computer Society’s Publications Board, and on various technology advisory or working groups including the International Technology Roadmap for Semiconductors (ITRS), Prof. Cheng has been internationally known as an eminent member of the field.

   In 2020, he received HK$443.9 million funding from the Hong Kong government’s InnoHK research clusters initiative to lead the founding of the AI Chip Center for Emerging Smart Systems for which four world-renowned universities participate. The multidisciplinary center aims to advance IC design to help realize ubiquitous AI applications in society.

Mehdi B. Tahoori, KIT, Germany, IEEE Fellow

Abstract:

   With increasing system complexity together with stringent runtime requirements for functional safety, the reliable and secure operation of electronics in safety-critical, enterprise servers and cloud computing domains become even more challenging. This is further exacerbated with nanoscale effects originating from new device structures and complex fabrication processes in advanced nodes. While traditionally design time and test time solutions were supposed to guarantee the in-field dependability and security of electronic systems, due to complex interaction of runtime effects from running workload and environment, there is a great need for a holistic approach for silicon lifecycle management, spanning from design time to in-field monitoring and adaptation.   This talk discusses the requirements and trends, as well as the opportunities and challenges of SLM for complex chips and systems fabricated in advanced nanoscale technology nodes.

Bio:

   Mehdi B. Tahoori is Professor and the Chair of Dependable Nano-Computing at Karlsruhe Institute of Technology (KIT), Germany. He received the B.S. degree in computer engineering from Sharif University of Technology, Tehran, Iran, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 2002 and 2003, respectively. He is currently the deputy editor-in-chief of IEEE Design and Test Magazine. He was the editor-in-chief of Elsevier Microelectronic Reliability journal. He was the program and general chair of IEEE VLSI Test Symposium in (VTS) and General Chair of IEEE European Test Symposium (ETS). Prof. Tahoori was a recipient of the US National Science Foundation Early Faculty Development (CAREER) Award in 2008 and European Research Council (ERC) Advanced Grant in 2022. He has received a number of best paper nominations and awards at various conferences and journals. He is currently the chair of IEEE European Test Technologies Technical Council (eTTTC). He is a fellow of the IEEE.

Xuan Zeng, Fudan University

Abstract:

   The analog integrated circuit design faces the challenges of enormous circuit scale, vast design space and complex design performance. High-dimensional nonlinear optimization and high-dimensional multi-objective optimization face the challenges of high modeling complexity, curse of dimensionality and difficulty in achieving convergence in nonlinear global optimization. In this keynote speech, we will present subspace based DFO innovative approaches to address the high-dimensional optimization problems encountered in analog integrated circuit synthesis. Firstly, an efficient batch Bayesian and Gaussian process enhanced subspace derivative free optimization method (BBGP-sDFO) is presented for high-dimensional analog circuit sizing. The proposed method reduces any high-dimensional analog circuit sizing problem into an effective 2-dimensional subspace. The proposed method BBGP-sDFO achieves 2.05× ∼ 17.65× simulation number speedup and 1.37× ∼ 16.11× runtime speedup compared with the state-of-the-art optimization methods. Secondly, a novel high-dimensional multi-objective optimization method via adaptive gradient-based subspace sampling (HiMOSS) is presented. The proposed HiMOSS method integrates previous gradients and previous iterations into the adaptive subspace through multi-variate Gaussian distribution. The subspace is constructed with gradients and previous success steps with their significance decaying over iterations. Compared to multi-objective method NSGA-II, HiMOSS achieves a 2.56× ~ 4.32× simulation number speedup and a 2.48× ~3.39× total runtime speedup reaching similar hypervolume for ACCIA and OTA circuit. Compared to multi-objective method MOEA/D, the proposed method achieves 7.72× and 5.19× simulation number speedups for ACCIA and OTA circuits. The proposed HiMOSS achieves better optimization results compared to the state-of-the-art high dimensional multi-objective methods. Finally, a constrained Voronoi tree-based domain decomposition method for high-dimensional Bayesian optimization is presented. The proposed cVTS algorithm achieves 11.6 times runtime speedup compared to the state-of-the-art method, making it a promising technique for high-dimensional analog circuit design automation.

Bio:

   Xuan Zeng (Senior Member, IEEE) received the B.S. and Ph.D. degrees in electrical engineering from Fudan University, Shanghai, China, in 1991 and 1997, respectively. She was a Visiting Professor with the Department of Electrical Engineering, Texas A&M University, College Station, TX, USA, in 2002, and the Microelectronics Department, Technische Universiteit Delft, Delft, The Netherlands, in 2003. From 2008 to 2012, she was the Director of the State Key Laboratory of Application Specific Integrated Circuits (ASIC) and Systems, Fudan University, where she is currently a Full Professor with the Microelectronics Department. Her current research interests include analog circuit modeling and synthesis, design for manufacturability, high-speed interconnect analysis and optimization, and circuit simulation. Prof. Zeng received the Changjiang Distinguished Professor with the Ministry of Education Department of China in 2014, the Chinese National Science Funds for Distinguished Young Scientists in 2011, the First-Class of Natural Science Prize of Shanghai in 2012, the 10th For Women in Science Award in China in 2013, and the Shanghai Municipal Natural Science Peony Award in 2014. She also received the Best Paper Award from the 8th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference 2017. She is an Associate Editor of the IEEE Transactions on Circuits and Systems—Part II: Express Briefs, the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and the ACM Transactions on Design Automation of Electronic Systems.

Fei Su

Biography :

Dr. Fei Su is a senior architect at Intel Corporation, leading R&D in DFX (Design for Testability and Dependability) and Telemetry/SLM (Silicon Lifecycle Management) architecture and methodology. With over 18 years of experience in the semiconductor industry, he has been involved in key phases of IP and SOC (System-on-Chip) development, including architecture, design, validation, and manufacturing testing. Dr. Su is also recognized as an accomplished researcher in emerging computing technology fields with publications, including a book, multiple book chapters, and over 60 papers in IEEE/ACM conferences and journals. He is the inventor of three granted patents, with three more pending. He has received awards such as the Best Paper Award at the IEEE International Conference on VLSI Design and the Outstanding Young Author Award from the IEEE Circuits and Systems Society. His research interests span architecture-level and circuit-level innovation, focusing on testability and dependability in various domains, including AI/ML hardware, cyber-physical systems and biochips, datacenter/high-performance computing, and autonomous systems.

Dr. Su actively contributes to cross-industry standardization efforts and plays a pivotal role in the technical ecosystem/community building, including development of the new IEEE workshops in the emerging fields. Dr. Su serves as an editorial board member for IEEE Design & Test (D&T) and has participated in organizing and technical program committees for several IEEE/ACM conferences. He has established strong research collaborations with top-tier universities and has been recognized with the SRC (Semiconductor Research Corporation) Outstanding Liaison Award in 2021 for his contributions.

Dr. Su received his B.S. and M.S. degrees in Automation from Tsinghua University in 1999 and 2001, respectively. He obtained his Ph.D. in Electrical and Computer Engineering from Duke University in 2006, where he received the Outstanding Dissertation Award from the European Design Automation Association (EDAA). He is a senior member of IEEE.

Yervant Zorian

Biography :

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.

Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Jyotika Athavale

Biography :

Jyotika Athavale is a Director, Engineering Architecture at Synopsys, leading quality, reliability and safety research, pathfinding and architectures for data centers and automotive applications. She also serves as the 2024 President of the IEEE Computer Society, overseeing overall IEEE-CS programs, operations and service to the global computing community.

Jyotika leads and influences several international standardization initiatives in the area of RAS/safety in IEEE, ISO, SAE, JEDEC and OCP. She led the development of the IEEE 2851-2023 standard on Functional Safety Data Format for Interoperability, and now chairs the IEEE P2851.1 standardization initiative on Functional Safety interoperability with reliability. For her leadership in international safety standardization, Jyotika was awarded the 2023 IEEE SA Standards Medallion. And for her leadership in service, she was awarded the IEEE Computer Society Golden Core Award in 2022.

Jyotika has authored patents and many technical publications in various international conferences and journals. She has also pioneered & chaired international workshops and conferences in the field of dependable technologies.

Aijiao Cui

Biography :

Aijiao Cui received the B.Eng. and M. Eng. degrees in electronics from Beijing Normal University, Beijing, China, in 2000 and 2003, respectively, and the Ph.D. degree in electrical and electronic engineering from Nanyang Technological University, Singapore, in 2009. From July 2003 to December 2004, she was a Lecturer with Beijing Jiaotong University, Beijing. She was a Research Fellow with Peking University Shenzhen SoC Laboratory, Shenzhen, from 2009 to 2010 prior to joining the School of Integrated Circuits of Harbin Institute of Technology (Shenzhen) in 2010, where she is currently a Professor. Her current research interests include hardware security and trusted IC design.

Gang Qu

Biography:

Gang Qu received the Ph.D. degree in computer science from the University of California, Los Angeles. He is currently a Professor with the Department of Electrical and Computer Engineering and the Institute for Systems Research, University of Maryland at College Park, where he leads the Maryland Embedded Systems and Hardware Security (MeshSec) Lab and the Wireless Sensors Laboratory. His primary research interests are in the area of embedded systems and VLSI CAD with a focus on low power system design and hardware related security and trust. Dr. Qu is a major contributor to the establishment of hardware security community. He has published more than 300 papers and delivered more than 150 keynotes, invited talks, and tutorials, most of them are on hardware security. He is a co-founder of the Asian Hardware-Oriented Security and Trust (AsianHOST) symposium in 2016, the Top Picks in Hardware and Embedded Security Workshop (Top Picks) in 2018, and the IEEE CEDA Hardware Security and Trust Technical Committee (HSTTC) in 2020. He has introduced hardware security track and served as track chair for many conferences, including DAC, ICCAD, ASPDAC, HOST, GLSVLSI (founding chair), SOCC (founding chair), and ISQED. He is an enthusiastic teacher, and has taught and co-taught various security courses. He is a fellow of IEEE.